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Cadence Design Systems, Inc. Sr Physical Design Methodology and Automation (P&R Backend) in San Jose, California

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Principal Design Engineer – Tensilica IP Backend Physical Design

The Cadence Tensilica Processor Core is used in high performance blocks of complex SoC's. This is one of the best-kept secrets within the semi IP world, powering AR/VR, HiFi Audio and Speech, Vision, Imaging and hundreds of intelligent IoT applications. The Tensilica processor family contains the next generation of embedded cores that meet the demands of AI/ML edge computing. We are extending the reach of our platform to help companies like Amazon, Facebook, Google, Microsoft and Intel embed our core into their product portfolios. Come be part of the next explosion of embedded devices building a key part of our processor generating platform for CPU's and DSP's.

Position Description:

Searching for an intelligent, inventive, self-starting engineer interested in developing new backend flow methodologies with the Cadence EDA toolset. You will be joining a small team of capable individuals with significant visibility throughout the entire Tensilica IP group within Cadence. You have a strong understanding of all stages of placement, CTS, routing, extraction and timing signoff, with a goal of optimizing power/performance/area of complex multi-processor Tensilica subsystems. Experience with the latest process technologies and concepts (CNOD leakage, via pillars, layer promotion, etc.) a plus.

Responsibilities:

  • Develop and maintain the Innovus-based place-and-route flow for our Tensilica processor IP product line, including floor-/power-planning of large (>40M gate) multicore solutions

  • Collaborate with the RTL design team to determine PPA tradeoffs for different processor architecture options

  • Participate in occasional benchmarking exercises for customer engagements

Requirements:

  • MSEE / MSCS and at least 5 years of experience with EDA flow development and usage

  • Strong understanding of digital logic design and computer architecture

  • An inquisitive, inventive mind

  • Excellent verbal and written communication skills

High value additional skills:

  • Knowledge of Perl, Make, and TCL scripting

  • Experience with low power techniques (PSO) using UPF or CPF

  • Experience with the Cadence digital EDA toolset (Genus / Innovus / Quantus / Tempus / Conformal) in the latest FinFET technologies

    We’re doing work that matters. Help us solve what others can’t.

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. 
Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

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